The use of GaN as a channel material in the fabrication of CMOS devices has been found to provide CMOS devices with a lower drain-source resistance (Rdson) because GaN provides improved carrier mobility and has a wider band gap. However, one of the problems with using GaN is the limited availability of suitable substrates for epitaxial growth. For example, a defect free and useful epitaxial deposition of GaN is achievable only on a 111 Si substrate, while CMOS is typically processed on a 100 Si substrate. Since CMOS cannot be integrated onto a 111 Si substrate due to defect issues, this places practical constraints on using GaN in conjunction with CMOS on a 100 Si substrate.
A need therefore exists for methodology enabling fabrication of a CMOS device and a GaN PA structure on a 100 Si substrate having a 111 surface orientation.